With development of semiconductor processes, a quantity of transistors that may be integrated on a chip is increasing, and to reduce power consumption and heat dissipation while improving performance, an architecture designer puts forward a thread-level coarse-grained parallel on-chip multi-core/many-core processor. The on-chip multi-core/many-core processor refers to a multi-core/many-core processor integrated on a same chip, and compared with a conventional multiprocessor, the on-chip multi-core/many-core processor has advantages of a higher on-chip bandwidth, a shorter communication distance, and a more rapid transmission speed, so that efficiency of data communication among multiple threads is higher.
However, when multiple threads are executed in parallel, a variable may be shared by the multiple threads. To ensure correctness of program execution semantics, a method for mutually-exclusively operating multiple threads is used, and the method can ensure that when multiple threads perform a read/write operation on shared memory, only one thread exclusively occupies the shared memory at a moment. Performance of the mutually-exclusive operation is very important to an on-chip multi-core/many-core processor, and directly affects a speed of collaborative execution of multiple threads.
A manner for implementing a mutually-exclusive operation in the prior art includes: setting a flag bit in memory outside a chip, where a flag bit 0 identifies that a lock is currently in an idle state, and a flag bit 1 identifies that the lock is currently in an occupied state. The lock is a mechanism that ensures only one thread operation is protected at a moment in multiple threads. When there is a mutually-exclusive operation, multiple small cores on the multi-core/many-core processor poll a same flag bit in the memory, and only when the flag bit is 0, that is, only when the lock is in an idle state, can the thread acquire the lock to further occupy the memory to perform a read/write operation, and at the same time, sets the flag bit to 1. If it is found that the flag bit is 1, the flag bit is queried again after a period of time. Although the method can implement the mutually-exclusive operation, accessing a flag bit outside the chip by a small core on the chip may generates a problem of larger system overheads, and constant polling of the flag bit may also impose a great pressure on an on-chip network.
Another manner for implementing a mutually-exclusive operation in the prior art includes: centrally processing, by using a synchronization management apparatus connected to multiple small cores shown in FIG. 1, mutually-exclusive requests of all small cores on the multi-core/many-core processor, that is, managing, by using the synchronization management apparatus, a lock application message for applying for a lock and a lock release message for releasing a lock that are of each small core, and determining, according to a state of a lock in the synchronization management apparatus, whether to obtain a lock or wait for a lock. The method can avoid larger system overheads generated by accessing a flag outside the chip, and avoid polling of the flag bit, but because all threads are managed by one synchronization management apparatus, increasing of a quantity of threads may cause a congestion phenomenon prolong a wait time of the threads, and reduce a speed of collaborative execution of the threads.